The present invention relates to a semiconductor memory device, in particular, a semiconductor memory device which is provided with a Roll Call circuit, for example in a shifting type redundant circuit, for determining if a redundant function is in operation.
As a semiconductor memory has grown in size in recent years, a memory device provided with redundant memory cells in addition to normal memory cells is widely employed so that the redundant memory cells can replace with defective memory cells in a regular memory cell array so as to avoid a chip to become defective. As a redundant circuit to replace a defective memory cell with a redundant memory cell, a shifting type redundant circuit in which the defective memory cell and its succeeding memory cells are sequentially shifted is commonly used.
A decoder circuit 9 in a general purpose DRAM is explained in the following as an example of a shifting type redundant circuit in the prior art with reference to FIGS. 12 to 15. As shown in FIG. 12, the decoder circuit 9 includes a redundant fuse 1, a Roll Call circuit 2, a column decoder 3, a column decoder switching circuit 4 and a column driver 5.
The redundant fuse 1 comprises a fuse wiring FL on which fuses F1 to F4 capable to be cut off are connected in series, a fuse driver 6 connected with one end of the fuse wiring FL for transmitting a signal to the fuse wiring FL, a fuse clamp 7 connected with the other end of the fuse wiring FL for preserving electric potential of the fuse wiring FL, and inverters INV1 to INV4.
The input of the inverter INV1 is a fuse node FN1 while the output thereof is a node N1, both of which are positioned between the fuse F1 and the fuse F2. The input of the inverter INV2 is a fuse node FN2 while the output thereof is a node N2, both of which are positioned between the fuse F2 and the fuse F3. The input of the inverter INV3 is a fuse node FN3 while the output thereof is a node N3, both of which are positioned between the fuse F3 and the fuse F4. The input of the inverter INV4 is a fuse node FN4 while the output thereof is a node N4, both of which are positioned between the fuse F4 and the fuse clump 7. The outputs from the output nodes N1 to N4 of the inverters INV1 to INV4 are transmitted as the outputs from the redundant fuse 1. Output from the redundant fuse 1 is input to the Roll Call circuit 2 and the column decoder switching circuit 4.
As shown in FIG. 14, the fuse clump 7 comprises a P-channel MOS transistor (hereinafter referred to as "PMOS") 7a connected with a power source, a PMOS 7b and an inverter 7c. When an enable signal FUSE-EN is at low level, the PMOS 7a is on, whereas when the enable signal FUSE-EN is at high level, the PMOS 7b is turned on through the inverter 7c so as to preserve the fuse wiring FL at high level.
The Roll Call circuit 2 is provided for the purpose of detecting if the redundant function is in operation. The Roll Call circuit 2 includes a wiring FL2 outputting the output RCY of the Roll Call circuit 2, inverters INV21 to INV24, inputs of which are the output nodes N1 to N4 of the redundant fuse 1, respectively, Nch transistors NT3, NT6 NT9 and NT12, inputs of which are the output nodes N9 to N12 of the inverters INV21 to INV24, respectively, a Nch transistor NT2 connected with the power source, Nch transistors NT5, NT8 and NT11, input of which are the output nodes N1 to N3, respectively, inverters INV25 to INV28, inputs of which are the output nodes N13 to N16 of NAND elements NAND 13 to NAND 16 of the column decoder 3, Nch transistors NT1, NT4, NT7 and NT10, inputs of which are the output nodes N5 to N8 of the inverters INV25 to INV28, a Roll Call clump circuit 8 for preserving the electric potential of the output RCY. The Nch transistors NT1 to NT3, NT4 to NT6, NT7 to NT9 and NT10 to NT12 are connected in series by threes. The nodes at one end are connected to GND, while the nodes at the other ends are connected with the output RCY.
As shown in FIG. 15, the Roll Call clump 8 includes a P-channel MOS transistor 8a connected to the power source, PMOS 8b, and an inverter 8c. When an enable signal RCY-EN is at low level, the PMOS 8a is on, whereas when the enable signal RCY-EN is at high level, the PMOS 8b is turned on through the inverter 8c so as to preserve the fuse wiring FL2 at high level.
The column decoder 3 comprises the NAND elements NAND 13 to NAND 16 for decoding column addresses. As mentioned above, the outputs from the NAND elements NAND 13 to NAND 16 are input to the Roll Call circuit 2, more precisely, to the Nch transistors NT1, NT4, NT7 and NT10 through the inverter elements INV25 to INV28. Furthermore, the outputs from the NAND elements NAND 13 to NAND 16 are input to the column decoder switching circuit 4, which will be explained below.
The column decoder switching circuit 4 comprises transfer gate T1 to T8 and inverters INV5 to INV8 for switching the direction of the outputs from the column decoder 3 by means of the output nodes N1 to N4 of the redundant fuse 1, and inverters INV9 to INV13 positioned on the wiring which output signs transmitted through the transfer gates T1 to T8 to the column driver 5.
If the node N1, which is the output of the redundant fuse 1 is at high level, the selection decoder output node N13 of the NAND element NAND 13 in the column decoder 3 is output to the node N17 through the transfer gate T1 and inverter INV9 by turning on the transfer gate T1. On the contrary, if the node N1 is at low level, the selection decoder output node N13 is output to the node N18 through the transfer gate T2 and inverter INV10 by turning on the transfer gate T2 through the inverter INV5.
Similarly, if the node N2, which is the output of the redundant fuse 1 is at high level, the selection decoder output node N14 of the NAND element NAND 14 is output to the node N18 through the transfer gate T3 and inverter INV10 by turning on the transfer gate T3. On the contrary, if the node N2 is at low level, the selection decoder output node N14 is output to the node N19 through the transfer gate T4 and inverter INV11 by turning on the transfer gate T4 through the inverter INV6.
If the node N3, which is the output of the redundant fuse 1 is at high level, the selection decoder output node N15 of the NAND element NAND 15 is output to the node N19 through the transfer gate T5 and inverter INV11 by turning on the transfer gate T5. On the contrary, if the node N3 is at low level, the selection decoder output node N15 is output to the node N20 through the transfer gate T6 and inverter INV12 by turning on the transfer gate T6 through the inverter INV7.
If the node N4, which is the output of the redundant fuse 1 is at high level, the selection decoder output node N16 of the NAND element NAND 16 is output to the node N20 through the transfer gate T7 and inverter INV12 by turning on the transfer gate T7. On the contrary, if the node N4 is at low level, the selection decoder output node N16 is output to the node N21 through the transfer gate T8 and inverter INV13 by turning on the transfer gate T8 through the inverter INV8. As the outputs from the column decoder switching circuit 4, the output from the nodes N17 to N21 of the inverters INV9 to INV13 are input to the column driver 5.
The column driver 5 comprises NAND elements NAND 51 to NAND 60 for conducting final decoding based on outputs from the decoders transmitted from the column decoder switching circuit 4, and inverters INV51 to INV60 for driving column lines. Due to the heavy load of the wiring capacity, generally, the column lines can not be driven directly by the output from the decoder so that the NAND elements NAND 51 to NAND 60 and the inverters INV51 to INV60 are provided as the column drivers to receive the output from the decoder and drive the column lines.
When the output node N17 in the column decoder switching circuit 4 is at high level, and a column address AY0B is also at high level, the NAND element NAND 51 is turned to low level, and a normal column line CL0 is driven by the inverter INV51. On the other hand, when a column address AY0 is at high level, the NAND element NAND 52 is turned to low level, and a normal column line CL1 is driven by the inverter INV52.
Similarly, when the output node N18 in the column decoder switching circuit 4 is at high level, and a column address AY0B is also at high level, the NAND element NAND 53 is turned to low level, and a normal column line CL2 is driven by the inverter INV53. On the other hand, when a column address AY0 is at high level, the NAND element NAND 54 is turned to low level, and a normal column line CL3 is driven by the inverter INV54.
When the output node N19 in the column decoder switching circuit 4 is at high level, and a column address AY0B is also at high level, the NAND element NAND 55 is turned to low level, and a normal column line CL4 is driven by the inverter INV55. On the other hand, when a column address AY0 is at high level, the NAND element NAND 56 is turned to low level, and a normal column line CL5 is driven by the inverter INV56.
When the output node N20 in the column decoder switching circuit 4 is at high level, and a column address AY0B is also at high level, the NAND element NAND 57 is turned to low level, and a normal column line CL6 is driven by the inverter INV57. On the other hand, when a column address AY0 is at high level, the NAND element NAND 58 is turned to low level, and a normal column line CL7 is driven by the inverter INV58.
When the output node N21 in the column decoder switching circuit 4 is at high level, and a column address AY0B is also at high level, the NAND element NAND 59 is turned to low level, and a redundant column line RCL0 is driven by the inverter INV59. On the other hand, when a column address AY0 is at high level, the NAND element NAND 60 is turned to low level, and a redundant column line RCL1 is driven by the inverter INV60.
The circuit structure of a semiconductor memory device 500 provided with the decoder circuit 9 is explained in the following with reference to the FIG. 13. The decoder circuits 9 are provided so as to correspond to with a memory cell blocks 20 with redundant function. The outputs RCY of the Roll Call circuits 2 in each decoder circuit 9 are connected in series.
Next, the operation of the semiconductor memory device 500 in the prior art is explained with reference to FIG. 16. First, the operation in case that the fuses are not cut off, in other words, the redundant column lines RCL0, RCL1 are not used, is explained with reference to FIG. 16.
When the fuse enable signal FUSE-EN for enabling the column decoder to be ready for operation is switched from low to high level, the fuse nodes FN1 to FN4 on the fuse wiring FL are switched from high to low level. Further, the nodes N1 to N4 which are the outputs of the redundant fuse 1 are turned from low to high level by means of the inverters INV1 to INV4. Consequently, the transfer gates T1, T3, T5 and T7 among the transfer gates provided in the column decoder switching circuit 4 are turned on. It is to be noted that in this specification, the transfer gates T1, T3, T5 and T7, which are turned on by switching the nodes N1 to N4 to high level are referred to as "the upper transfer gates", whereas the transfer gates T2, T4, T6 and T8, which are turned on by switching the nodes N1 to N4 to low level are referred to as "the lower transfer gates".
If the output node N13 of the column decoder is selected by the column decoder and turned to low level after the upper transfer gates T1, T3, T5 and T7 are turned on, the node N17 is turned to high level through the transfer gate T1. Next, with the column address AY0B turned to high level, the column line CL0 is switched from low to high level. Similarly, as the nodes N18 to N20 are turned to high level, but the node N21 is not turned to high level in case that the fuses are not cut off, only the normal column lines CL0 to CL7 are used.
Next, the operation in case that the redundant column lines are used is explained with reference to FIG. 17. Here, the operation in case that the fuse F2 is cut off is explained as an example. When the fuse enable signal FUSE-EN is switched from low to high level, the fuse nodes FN1 is turned to low level, whereas the node N1 is turned to high level. As the fuse F2 is cut off, the fuse nodes FN2 to FN4 are preserved at high level, while the nodes N2 to N4 are preserved at low level by means of the fuse clump 7. Consequently, the transfer gates T1, T4, T6 and T8 are turned on. As a result, with the transfer gate T8 turned on, the node N21 is switched to high level, thereby the redundant column lines RCL0 and RCL1 are used in the place of the normal column lines CL2 and CL3.
Similarly, when the normal column lines CL0 and CL1 are released from operation by redundant function, the fuse F1 is cut off When the normal column lines CL4 and CL5 are released from operation by redundant function, the fuse F3 is cut off. When the normal column lines CL6 and CL7 are released from operation by redundant function, the fuse F4 is cut off. In a word, when a fuse is cut off, the column lines including the object of the redundant function and its succeeding column lines are shifted by one stage so that the redundant column lines RCL0 and RCL1 are used.
In the following, the operation of the Roll Call circuit 2 in case that the redundant column line is used due to the fuse F2 being cut off. The output node N6 of the inverter INV26 input of which is the output node N14 of the selected column decoder, is turned to high level, and the Nch transistor NT4, input of which is the output node N6 is turned on. The output node N1 of the fuse F1 is also at high level, and the Nch transistor NT5, input of which is the output node N1 is on. In addition, the output node N2 of the fuse F2 is at low level, and the Nch transistor T6, input of which is the output node N10 of the inverter INV22 with the output node N2 as its input, is also on.
As mentioned above, regarding the nodes N1 to N4 which function as the inputs of the Roll Call circuit 2, only the Nch transistors which are positioned where the nodes provided at the upstream thereof are at high level, and the nodes provided at the downstream are at low level are turned on. By turning on all the Nch transistors connected in series by threes, the output RCY which is output from the Roll Call circuit 2 is turned to low level. However, when the enable signal RCY-EN is turned from high to low level, the output RCY is turned from low to high level by means of the Roll Call clump 8. Thus, by monitoring the output RCY, it can be detected if the redundant function of the address is in operation, in other words, switching of the output RCY to low level indicates that redundant function is in operation.
However, the semiconductor memory device 500 in the prior art requires multiple Roll Call circuits, number of which must be equivalent to that of the fuses. In addition, the Roll Call clump is also required to control the output signal RCY of the Roll Call circuit. These necessitate a large pattern size.